The application of Partial Response Maximum Likelihood (herein after PRML) techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973. Applying PRML techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991.
In magnetic storage systems, a transducing head writes digital data onto the surface of a magnetic storage medium, such as a magnetic disk. The digital data serves to modulate the current in the head coil in writing a sequence of corresponding magnetic flux transitions which represent the digital data. When reading the recorded data, the head again passes over the magnetic medium and transduces the magnetic transitions into pulses in an analog read signal, which are then decoded by read channel circuitry to reproduce the digital sequence.
Decoding the pulses into a digital sequence can be performed by a simple pulse detector read channel or, as in more recent designs, by a partial response maximum likelihood (PRML) read channel. The PRML read channel scheme is preferred over the simpler pulse detection scheme because it decreases the necessary bandwidth, thereby allowing more data to be stored on the storage medium.
In conventional peak detection as well as PRML schemes, a channel code provides clocking and automatic gain control (AGC) information. To perform the timing and gain control, the number of consecutive zero samples must be limited since timing and gain control information is derived only when non-zero samples are read from the channel. Typically, an RLL code having a (d,k) constraint, which specifies the minimum and maximum run lengths of zeros respectively, encodes the data before recording it to the storage medium. For instance, a byte oriented (d=0, k=4) 8/9 code encodes binary data represented as 8 bit data bytes into 9 bit codewords in order to achieve the desired (d,k) constraint. Because he PRML technique utilizes inter-symbol interference (ISI) in a controlled manner, the d constraint in partial response class-IV channels is unnecessary (d=0). However the k constraint is still necessary in class-IV systems to provide the timing and gain control information.
The sampled data in partial response (PR) channels is typically converted into a digital sequence using maximum likelihood (ML) detection techniques (thus PRML). A Viterbi sequence detector normally implements the maximum likelihood Viterbi algorithm for detecting the digital sequence from the sampled data. See G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973,
Prior art implementations of encoders and Viterbi sequence detectors in Partial Response class-IV channels introduced an additional constraint on the number of consecutive zeros in each of the even and odd interleaves of the encoded data in order to minimize the path memory of the detector. Thus the conventional modulation codes for PR class-IV systems utilizing Viterbi detection are characterized by (d,k/k1) where k1 represents the maximum run length of zeroes in both the even and odd subsequences. A small value of k is desirable for accurate timing and gain control, and a small value of k1 reduces the size of the path memory in the Viterbi detector. A method for encoding the channel data according to the (d,k/k1) constraints is described in U.S. Pat. No. 4,707,681, the disclosure of which is herein incorporated by reference.
FIG. 3 shows an example trellis diagram for the 1-D.sup.2 PR class-IV channel and the effect the k1 constraint has on the path memory length of the Viterbi detector. As shown in the diagram, the path memories merge into one survivor sequence only after a "1" has been detected in both the even 40 and odd 42 interleaves. Therefore, in prior art implementations the length of the Viterbi detector path memories must be greater than 2(k1+1)+1 to guarantee that the paths merge into the correct sequence 34.
A further problem with the prior art implementations is that a minimum delay of 2(k1+1)+1 samples is required before the paths merge and the correct sequence is available. This latency degrades the performance of the storage systems; for instance, it increases the delay between reading the ID field and writing data to the disk. The latency also degrades the performance of other read channel components that use the output of the sequence detector, such as servo control.
Another problem with the prior art is the inability to correct errors in the data samples due to noise. For instance, if noise in the system causes a "1" to be erased, the path memories of the Viterbi detector may not be merged after 2(k1+1)+1 samples and the detected sequence may not be correct.
It is a general object of the present invention to provide a method and apparatus for processing data in a PR class-IV communication channel that does not require the conventional k1 constraint, thereby minimizing the path memory and latency of the Viterbi detector. Another object of the invention is to correct the errors in the detected sequence when a "1" is erased due to noise in the system.